Cadence Design Systems, Inc., a leader in global electronic design innovation, has released the hotfix of Cadence Allegro and OrCAD 17.0 design solution with new features, enhanced customization capabilities, and simulation performance improvements that provide customers a shorter, more predictable path to product creation. DATE: 07-31-2015 HOTFIX VERSION: 054
CCRID PRODUCT PRODUCTLEVEL2 TITLE
694479 CONCEPT_HDL OTHER Need version control of symbols in DE-HDL 695025 CONCEPT_HDL OTHER Version option of Add Component should filter mismatched versions 1004049 CONCEPT_HDL OTHER Grouping of PACK_TYPE specific symbols by version in Version and Version List 1357843 ALLEGRO_EDITOR PLACEMENT The net association of a via changes when a replicated circuit is placed using Place Replicate 1367917 CONCEPT_HDL CORE The PIN_TEXT property of a symbol increases in size when rotated at 90, 180, or 270 degrees 1405364 ALLEGRO_EDITOR EDIT_ETCH Slide Via snaps to the near by vias 1412635 APD DATABASE APD crashes on saving design 1413214 FSP FPGA_SUPPORT Need spreadsheet rules to support FPGA devices 1427732 SIG_INTEGRITY SIGNOISE Constraint Manager does not display results of Xtalk simulation 1430416 ORBITIO OTHER Importing a .sip database to OrbitIO should also import the shapes. 1435246 ALLEGRO_EDITOR SHAPE Shape shorts with signal net in artwork in SPB166 Hotfix 50 1437479 CONCEPT_HDL PDF The Publish PDF form appears truncated when the screen display is set to "Medium - 125%" 1438848 APD OTHER Layers of a module, mirrored using the Mirror Geometry command, change on refreshing the module 1439536 SCM IMPORTS On running Import Physical on a .sip file with a die abstract, wrong pin names are generated 1440332 ALLEGRO_EDITOR ARTWORK The oblong slot hole changes size in the IPC2581 output 1441408 PCB_LIBRARIAN VERIFICATION About Release command could not read NC_PINS property in Part Classification 1443224 CONCEPT_HDL CORE Rotated Text appears bigger in size compared to the normal text. 1444562 CONCEPT_HDL CORE Use of Synonym not shorting nets 1444932 ALLEGRO_EDITOR INTERFACES When exported to PDF, the octagonal pads in a padstack are larger than their size in Allegro PCB Editor 1445606 CONCEPT_HDL CORE Make the Component Revision Manager UI similar to LRM in ADW Flow 1445925 ORBITIO ALLEGRO_SIP_IF Merge Update of a SiP File failed 1446259 ALLEGRO_EDITOR INTERFACES Export PDF prints a big square box instead of a frectangle on the board 1446792 CONCEPT_HDL CORE BOM-HDL: How to output attributes attached to the instances of reuse blocks 1446866 ALLEGRO_EDITOR REPORTS IMPEDANCE_RULE values not being extracted in reports 1447863 FSP MODEL_EDITOR Ability to assign clock pin to QBC 1448802 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on routing across constraint region boundary 1449255 ALLEGRO_EDITOR OTHER Edit > Change causes Allegro PCB Editor to crash. 1450470 ALLEGRO_EDITOR EDIT_ETCH Return path vias: need provision to specify spacing value of less than 1
Name: Cadence SPB OrCAD Version: (32bit) 16.60.054 Hotfix Home: www.cadence.com Interface: english OS: Windows XP / Vista / Seven System Requirements: Cadence SPB OrCAD 16.60.000 - 16.60.053
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Cadence SPB OrCAD 16.60.054 Hotfix
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